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Study and Analysis of a QFN Packaged 8-Bit Phase Shifter Design Using 65-nm CMOS Technology

Arthi. R, S. Christopher, R. David Koilpillai

A digital 8-bit phase shifter using 65-nm CMOS technology for a band of 3 GHz -4 GHz is designed, fabricated and tested. This work is based on the switched line topology utilizing various combinations of filters with lumped components for achieving the desired performance. Though in the simulation the tolerances with respect to the requirement is much better when it comes to packaging it deteriorates due to uncertainties. Thus, this work aims to study the effect of bond wire on the phase shifter in a packaged condition. The insertion loss variation and the return losses are affected by the lead inductance but the phase performance remains more or less same as the design. The fabricated 8-bit phase shifter demonstrates an overall rms phase error less than 2.17⁰ over the band 3 GHz-4 GHz for all the 256 states. The insertion loss is increased by 4.76 dB for the reference state for the packaged chip and the variation in the insertion loss being ± 10 dB over all the states in the entire band. The measured input and output matching of the packaged chip are less than -4 dB and–6 dB over the entire band respectively