抽象的な

Radix-2 CORDIC Method with Constant Scale Factor

J. M. Rudagi, Vinayak Dalavi

There are various simple hardware-efficient algorithms exist which can be used to increase speed while performing the desired signal processing tasks. One such simple and hardware-efficient algorithm is CORDIC which uses only Shift-and-Add arithmetic with table Look-Up to implement different functions. It can be used to efficiently implement Trigonometric and other functions. In this paper we present the conventional unrolled CORDIC architecture. The processor is designed using Verilog HDL using a structured coding method, simulated using ISIM simulator and implemented using Xilinx 14.2 FPGA synthesis Tool for 16 and 32 bit conventional radix-2 CORDIC architectures. The output of the CORDIC architectures are analyzed and verified, and compared with the actual values obtained from MATLAB.