抽象的な

Performance Enhancement of AES Algorithm Using Dynamic Partial Reconfiguration

Ms.Snehal Wankhade, Prof. Rashmi Mahajan

This work reports Partial Reconfiguration (PR) by which FPGA can dynamically reconfigure. The concept of self-reconfiguration is tried to explain under the control of embedded microprocessor like microblaze. Here PR could be useful to reduce area requirements and upsurge systems versatility. Partial Reconfiguration is supported on high end FPGAs like Sparten III, Virtex series. Today cryptographic algorithms are not safe also embedded cryptographic hardware is costly. Hence to make it cost effective and to provide more secureness reconfigurable hardware such as FPGA can be used. In this project AES (Advanced Encryption Standard) algorithm has been selected for PR implementation to achieve the goal of secureness in cryptography. This work gives briefings about the method of hardware implementation for AES encryption algorithm with Dynamic Partial Reconfigurable keys. This implementation could be a good solution to preserve confidentiality and convenience to the information in the numeric communication.