抽象的な

Dynamic Shift Scan with Area Efficiency

Sequential circuit testing is more effective if it is done using dynamic shift scan method. Again the testing of sequential circuits can be done in minimum clock cycles by using a cycle cycle access with hold mode. Here the advantage is it reduces the clock cycles and the problem is it increases the hardware. The percentage of utilization again can be reduce by the modification of scan cells. Each scan cells can be change to single cycle access without hold mode. It reduces the clock cycles and reduces the area utilization also.