抽象的な

DESIGN AND ANALYSIS OF LOW POWER COMPRESSORS

S.Karthick, S.Karthika, S.Valarmathy

The power management has become a great concern due to the increased usage of multimedia devices. Multipliers are the main sources of power consumption in these devices. The 3-2, 4-2 and 5-2 compressors are the basic components in many applications like partial product summation in multipliers. In this paper, various types of compressors have been designed. Different logic styles of XOR-XNOR gates and multiplexers have been compared with the existing CMOS logic. The pass transistor implementation of XOR-XNOR gates and multiplexer circuits achieves low power with less number of transistor counts. The proposed compressor architecture can be built using various combinations of XOR-XNOR gates, transistor level implementation and multiplexer circuits. The performance of basic compressor architectures with these low power XOR-XNOR gates and MUX blocks is found to be efficient in terms of area and power. Hence, the proposed 8x8-bit Wallace tree multiplier was designed using this proposed compressors and the power results are compared with the conventional Wallace tree multiplier design. The proposed Wallace tree multiplier using these compressors achieves significant amount of less power than conventional Wallace tree multiplier. The designs are implemented and power results are obtained using TANNER EDA 12.0 v tool.