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BP FIR FILTER IMPLEMENTATION ON FPGA USING FULLY PARALLEL AND DA ARCHITECTURE

Kavya Jyothi.B, Dr. K.B.Shivakumar , Dr.M.Z.Kurian, Prof. Imran Rasheed

Area occupied by an FIR(Finite Impulse Response) filter increases as the order of the filter increase. This is due to the increase in the number of multipliers in the parallely implemented MAC (Multiply and Accumulate) structure. This paper presents an efficient design for the implementation of BP FIR filter on FPGA (Field Programmable Gate Array) using DA (Distributed Arithmetic) architecture. DA replaces multipliers by LUTs( Look Up Tables), adders and shift registers. Hence optimal resource utilization is possible, as number of fully utilized LUT flip flop pair increases. In addition DA technique adopts pipelined processing of data. Hence throughput can be increased by increasing the number of pipelined stages. A verilog code is developed for the proposed design in Xilinx ISE 14.4. Later it is simulated on ISim simulator. Then it is implemented on FPGA Virtex 5 and verified using Chipscope Pro. Later the design is optimized for time, area and power. Design of FIR filter on FPGA has practical applications in high speed DSP computations, communication and image processing applications