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An Efficient Implementation of Double Precision Floating Point Multiplier Using Booth Algorithm

Pallavi Ramteke, Dr. N. N. Mhala, Prof. P. R. Lakhe

Floating-point numbers are widely adopted in many applications due to their dynamic representation capabilities. Basically floating point numbers are one possible way of representing real numbers in binary format. Multiplying floating point numbers is also a critical requirement for DSP applications involving large dynamic range. The IEEE 754 standard presents two different floating point formats, Binary interchange format and Decimal interchange format. This paper presents the floating point multiplier that supports the IEEE 754 binary interchange format. This paper mainly focuses on double precision floating point multiplier based on Booth algorithm. The main object of this paper is to reduce the power consumption and to increase the speed of execution by implementing certain algorithm for multiplying two floating point numbers. In order to design this, VHDL is used and targeted on a Xilinx Virtex-5 FPGA. The implementation��?s tradeoffs are area, speed and power. In this paper Shift and Add Multiplier is compared with Radix-4 Booth Multiplier. This multiplier also handles overflow and underflow cases. For high accuracy of the results normalization is also applied.