抽象的な

128-BIT CARRY SELECT ADDER HAVING LESS AREA AND DELAY

M.CHITHRA, G.OMKARESWARI

Design of low area, delay and power forms the largest systems in VLSI system design. Carry Select Adder (CSLA) is one of the fastest adders to perform arithmetic operations comparing all conventional adders. From the structure of CSLA there is a scope for reducing the area and delay. Based on the modification of 16, 32, and 64-bit Carry Select Adder (CSLA) architectures have been developed and compared with the regular CSLA architecture. A carry-select adder (CSLA) can be implemented by using Ripple carry adder. The proposed design 128-bit CSLA has reduced more delay and area as compared with the regular 128-bit CSLA. Results obtained from modified carry select adders are better in area, delay and power consumption.