抽象的な

Improvement of Voltage Stability Margin Using SVC

C.Muthamil Selvi,Dr.K.Gnanambal, P.Pon Ragothama Priya

The problem of voltage stability is one of the main concern in the operation of power systems. Voltage stability can be determined by determining the maximum loading point of the system. The estimation of voltage stability at various operating condition is essential to operate the system with sufficient safety margin. The objective of this project is to improve the static voltage stability of the power system using SVC emerging CPF algorithm. The voltages at various buses are calculated and the weak buses are identified to place the FACTS devices to improve the voltage stability margin of the system. The voltage stability limits are analyzed before and after the placement of SVC. The IEEE 9 bus system is considered as the test case for this analysis.