抽象的な

Implementation of Multi-Resolution On-Chip AHB Bus Tracer with Real Time Lossless Compression

Dr. K. Babulu, P. Anvesh

An On-Chip AHB Bus Tracer is a significant infrastructure that is needed to monitor the on chip-bus signals, which is vital for debugging and performance analysis and also optimizing the SoC (System On Chip). So in this paper we implement the on-chip AHB bus tracer, that traces with different resolutions, i.e. with different signal and abstraction levels depending on the need to match with specific debug /analysis needs. In addition it allows the user to switch the resolution on-the-fly. Subsequently compression of the trace without any loss of the actual trace which when reconstructed at the analyser will remain the same. This Bus Tracer adopts three trace compression techniques to achieve high compression ratio. The On-Chip AHB bus tracer with Real-Time Compression and Dynamic Multi-Resolution was designed successfully; the RTL simulations were performed successfully along with successful synthesis using Xilinx ISE.