抽象的な

Energy Efficient and High Speed Charge-Pump Phase Locked Loop

Sherin Mary Enosh

This work implements an energy efficient and high speed phase locked loop (PLL) . The main block of PLL is Phase Frequency Detector (PFD), Charge Pump (CP), Low pass filter and a Voltage controlled Oscillator (VCO). The Phase frequency detector used here has been implemented with True Single Phase Clocked logic (TSPC) D flip-flop. This PFD is used to increase the locking performance and to reduce the dead zone. Charge pump is used for the DC-DC conversion. The proposed charge pump avoids charge injection, clock feed through effects and this reduces the ripples in the output. Ring oscillator is used as Voltage Control Oscillator which requires less layout area and has a wide frequency tuning range. Supply voltage of 3V is used and the power dissipated is 11.409 mW. TSMC 0.35- μm technology is used to implement the proposed phase locked loop.