抽象的な

Design Of Efficient Shift Register with Double Edge Triggered Flip-Flop

R.Vidhya, K.Bashkaran

Energy efficiency is an important factor in digital designs. A large amount of power consumption is due to storage elements and clock distribution networks. For storage elements, instead of using single edge triggered flipflop, Double Edge Triggered Flip-flop is used to save energy as they can maintain the same throughput with half of clock frequency. Clock gating is used to reduce the dynamic power consumption. Incorporating clock gating with double edge triggered flip-flop further reduces power consumption but introduces asynchronous data sampling. In proposed system, shift register is built with Double Edge Triggered flip-flop and the asynchronous data sampling is removed using in The circuit is simulated with Tanner Tool v14.1 and Modelsim 6.3f.