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CLOCKING STRATEGIES IN HIGH SPEED I/O USING PLL

Namita Jain

The normal clocking strategies are not applicable at very high frequencies due to the signal integrity problems. The speed of any high speed circuit is ultimately determined by the I/O circuits associated with it. This paper describes a comparison between different clocking strategies and gives a range of application of these. During 1970-1990, gates switched so slowly that - digital signals actually looked like ones and zeros. Analog modeling of signal propagation was not necessary. At today’s speeds the simple, passive elements of a system viz, Wires, PC boards traces, Connectors, and Chip Packages - make up a significant part of the overall signal delay. Further these elements cause glitches, resets, logic errors, and other problems. As the designs are pushed towards higher operating speeds. For high-performance boards, MCMs and systems, interconnect design must be specified and driven from electrical requirements to: (1)Meet setup and hold times & guarantee signal integrity (2)Avoid design / layout / verification iterations (3)Ensure low manufacturing costs and high reliability The conventional signaling technique, called Common Clock (CC) signaling [support by reference], relies on a single system clock distributed to all bus agents as a common reference. All transactions are performed latch-to-latch using this common clock reference. Trace propagation delays are governed by trace length. Trace lengths are often governed by the thermal solution. As speeds increase, heat sinks get larger and force components farther away from each other, which limit the speed of a common-clock bus design. Source-Synchronous clocking refers to the technique of sourcing a clock along with the data. Specifically, the timing of unidirectional data signals is referenced to a clock (often called the strobe) sourced by the same device that generates those signals, and not to a global clock (i.e. generated by a bus master). A reason that source-synchronous clocking is useful is that it has been observed that all of the circuits within a given semiconductor device experience roughly the same process-voltage-temperature (PVT) variation. This means signal propagation delay experienced by the data through a device tracks the delay experienced by the clock through that same device over PVT A more radical approach for reducing the clocking overhead is to eliminate the clock entirely. Such designs are called self-timed designs. Self-timed systems provide completion information along with their data values. This completion information controls the sequencing of data through the machine and can be encoded in the data (true self-timing) or can be generated by using delay-matching circuits.