抽象的な

A VALIDATION OF SIM-A WITH OVPSIM

Gajendra Kumar Ranka, Dr. Manoj Kumar Jain

The design of modern embedded systems requires automated modelling tools for faster design and for the study of various design tradeoffs. Such tools put together constitute an integrated environment where the designer can write the high level design specifications in a language and use these tools for automatic generation of system specific tools. The major contribution of this paper lies in design and development of retargetable simulator and validation of the simulator with different simulators like OVPSim {Open Virtual Platform}. Proposed simulator measures cycle count for application executed on processor. This paper discusses the OVP Simulators, its working and the different customisations that are required to execute the benchmark application on this Simulator.